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 Заголовок сообщения: the "Switcheroo" cipher
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I designed a stream cipher that I call the Switcheroo. The idea is that an instruction can be added to an FPGA processor to encrypt/decrypt a bit. Hopefully this instruction can take only 4 clock cycles. It uses a 96-bit key, all of which should be held in registers.

I don't really know anything about cryptoanalysis. I was originally going to use an Alternating Stop-and-Go cipher, but then I invented this that might be slightly easier to implement. If anybody here knows anything about cryptoanalysis, perhaps you can offer an opinion on how secure this is. AFAIK, 128 bits is the minimum for a "strong" encryption system, with 256 bits being more common. My 96-bit key may seem small by modern standards.

I can write some Forth code to simulate it, but I haven't done so yet.

These are the resources:
There are three 32-bit seeds, each of which must be nonzero. They are: A, B, C
We have two 1-bit registers for temporary use, which are: CF and NZ

Seed A can be clocked as an LFSR with the result going into the CF 1-bit register.
CF= (XOR bit-7, bit-5, bit-3, bit-2, bit-1, bit-0). CF is then shifted into the top

This is the algorithm:
clock A
If CF is 1 then:
        switch A <--> B
        set NZ= bit-0 of C
        switch A <--> C
        set NZ= bit-0 of B
clock A
return CF xor NZ as the result

The reason why this is simpler than the Alternating Stop-and-Go is that we only have to work with seed-A as an LFSR. Seeds B and C are switched into seed A as necessary, but are not clocked directly.

With an Alternating Stop-and-Go cipher, we are advised to make each of the three LFSRs different sizes. In mine, all three are the same size: 32-bit. I don't think that this is a weakness. A 32-bit LFSR rolls over at 1/2 gigabyte of data --- that is a lot! --- I might have files of a few megabytes at the most.

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