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Начиная с num_conv.spf начинаются проблемы.
Куда смотреть?
Какие именно проблемы?
Первое, что приходит в голову - правильно ли заданы области памяти? Покажите файл описания девайса
Файл пока не причёсан:
Код:
\ ATMega2560 INITIALIZATION
( atmega2560 )
mega2560 CONSTANT DEVICE
0x40000 TO ROM-SIZE \ FLASH
0x0100 TO RAM-BOTTOM \ начало RAM
0x2000 TO RAM-SIZE \ размер RAM
RAM-BOTTOM RAM-SIZE + 1- TO RAM-TOP \ конец RAM, дно стека возвратов
0x0100 TO RSTACK-SIZE \ размер стека возвратов
RAM-TOP RSTACK-SIZE - 1+ TO SPTR0 \ дно стека данных
0x2 TO VECTOR-SIZE \ размер вектора прерываний в байтах
HAS_MOVW \ поддерживается инструкция movw
HAS_MUL \ есть команда умножения
\ ANALOG_COMPARATOR
0x7B == ADCSRB \ ADC Control and Status Register B
0x40 == ADCSRB_ACME \ Analog Comparator Multiplexer Enable
0x50 == ACSR \ Analog Comparator Control And Status Register
0x80 == ACSR_ACD \ Analog Comparator Disable
0x40 == ACSR_ACBG \ Analog Comparator Bandgap Select
0x20 == ACSR_ACO \ Analog Compare Output
0x10 == ACSR_ACI \ Analog Comparator Interrupt Flag
0x08 == ACSR_ACIE \ Analog Comparator Interrupt Enable
0x04 == ACSR_ACIC \ Analog Comparator Input Capture Enable
0x03 == ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
0x7F == DIDR1 \ Digital Input Disable Register 1
0x02 == DIDR1_AIN1D \ AIN1 Digital Input Disable
0x01 == DIDR1_AIN0D \ AIN0 Digital Input Disable
\ USART0
0xC6 == UDR0 \ USART I/O Data Register
0xC0 == UCSR0A
0x7 == RXC
0x6 == TXC
0x5 == UDRE
0x4 == FE
0x3 == DOR
0x2 == UPE
0x1 == U2X
0x0 == MPCM
0xC1 == UCSR0B \ USART Control and Status Register B
0x7 == RXCIE
0x6 == TXCIE
0x5 == UDRIE
0x4 == RXEN
0x3 == TXEN
0x2 == UCSZ2
0x1 == RXB8
0x0 == TXB8
0xC2 == UCSR0C
0x7 == UMSEL1
0x6 == UMSEL0
0x5 == UPM1
0x4 == UPM0
0x3 == USBS
0x2 == UCSZ1 0x2 == UDORD0
0x1 == UCSZ0 0x1 == UCPHA0
0x0 == UCPOL
0xC4 == UBRR0L
0xC5 == UBRR0H
\ TWI
0xBD == TWAMR
0x7 == TWAM6
0x6 == TWAM5
0x5 == TWAM4
0x4 == TWAM3
0x3 == TWAM2
0x2 == TWAM1
0x1 == TWAM0 0xFE == TWAMR_TWAM \
0xB8 == TWBR
0xBC == TWCR
0x7 == TWINT
0x6 == TWEA
0x5 == TWSTA
0x4 == TWSTO
0x3 == TWWC
0x2 == TWEN
0x0 == TWIE
0xB9 == TWSR
0x7 == TWS7
0x6 == TWS6
0x5 == TWS5
0x4 == TWS4
0x3 == TWS3
0x1 == TWPS1
0x0 == TWPS0
0xBB == TWDR
0xBA == TWAR
0x7 == TWA6
0x6 == TWA5
0x5 == TWA4
0x4 == TWA3
0x3 == TWA2
0x2 == TWA1
0x1 == TWA0
0x0 == TWGCE
\ SPI
0x4C == SPCR
0x7 == SPIE
0x6 == SPE
0x5 == DORD
0x4 == MSTR
0x3 == CPOL
0x2 == CPHA
0x1 == SPR1
0x0 == SPR0
0x4D == SPSR
0x7 == SPIF
0x6 == WCOL
0x0 == SPI2X
0x4E == SPDR
\ PORTA
0x22 == PORTA \ Port A Data Register
0x21 == DDRA \ Port A Data Direction Register
0x20 == PINA \ Port A Input Pins
\ PORTB
0x23 == PINB
0x24 == DDRB
0x25 == PORTB
0x26 == PINC
0x27 == DDRC
0x28 == PORTC
0x29 == PIND
0x2A == DDRD
0x2B == PORTD
\ PORTE
0x2E == PORTE \ Data Register, Port E
0x2D == DDRE \ Data Direction Register, Port E
0x2C == PINE \ Input Pins, Port E
\ PORTF
0x31 == PORTF \ Data Register, Port F
0x20 == DDRF \ Data Direction Register, Port F
0x2F == PINF \ Input Pins, Port F
\ PORTG
0x34 == PORTG \ Data Register, Port G
0x33 == DDRG \ Data Direction Register, Port G
0x32 == PING \ Input Pins, Port G
\ PORTH
0x102 == PORTH \ PORT H Data Register
0x101 == DDRH \ PORT H Data Direction Register
0x100 == PINH \ PORT H Input Pins
\ PORTJ
0x105 == PORTJ \ PORT J Data Register
0x104 == DDRJ \ PORT J Data Direction Register
0x103 == PINJ \ PORT J Input Pins
\ PORTK
0x108 == PORTK \ PORT K Data Register
0x107 == DDRK \ PORT K Data Direction Register
0x106 == PINK \ PORT K Input Pins
\ PORTL
0x10B == PORTL \ PORT L Data Register
0x10A == DDRL \ PORT L Data Direction Register
0x109 == PINL \ PORT L Input Pins
\ TIMER_COUNTER_0
0x46 == TCNT0
0x47 == OCR0A
0x48 == OCR0B
0x45 == TCCR0B
0x7 == FOC0A
0x6 == FOC0B
0x3 == WGM02
0x2 == CS02
0x1 == CS01
0x0 == CS00
0x44 == TCCR0A
0x7 == COM0A1
0x6 == COM0A0
0x5 == COM0B1
0x4 == COM0B0
0x1 == WGM01
0x0 == WGM00
0x6E == TIMSK0
0x6E == TIMSK
0x2 == OCIE0B
0x1 == OCIE0A
0x0 == TOIE0
0x35 == TIFR0
0x2 == OCF0B
0x1 == OCF0A
0x0 == TOV0
0x43 == GTCCR
0x7 == TSM
0x1 == PSRASY
0x0 == PSRSYNC
\ TIMER_COUNTER_2
0x70 == TIMSK2
0x2 == OCIE2B
0x1 == OCIE2A
0x0 == TOIE2
0x37 == TIFR2
0x2 == OCF2B
0x1 == OCF2A
0x0 == TOV2
0xB0 == TCCR2A
0x7 == COM2A1
0x6 == COM2A0
0x5 == COM2B1
0x4 == COM2B0
0x1 == WGM21
0x0 == WGM20
0xB1 == TCCR2B
0x7 == FOC2A
0x6 == FOC2B
0x3 == WGM22
0x2 == CS22
0x1 == CS21
0x0 == CS20
0xB2 == TCNT2
0xB3 == OCR2A
0xB4 == OCR2B
0xB6 == ASSR
0x6 == EXCLK
0x5 == AS2
0x4 == TCN2UB
0x3 == OCR2AUB
0x2 == OCR2BUB
0x1 == TCR2AUB
0x0 == TCR2BUB
\ WATCHDOG
0x60 == WDTCSR
0x7 == WDIF
0x6 == WDIE
0x5 == WDP3
0x4 == WDCE
0x3 == WDE
0x2 == WDP2
0x1 == WDP1
0x0 == WDP0
\ USART1
0xCE == UDR1 \ USART I/O Data Register
0xC8 == UCSR1A \ USART Control and Status Register A
0x80 == UCSR1A_RXC1 \ USART Receive Complete
0x40 == UCSR1A_TXC1 \ USART Transmitt Complete
0x20 == UCSR1A_UDRE1 \ USART Data Register Empty
0x10 == UCSR1A_FE1 \ Framing Error
0x08 == UCSR1A_DOR1 \ Data overRun
0x04 == UCSR1A_UPE1 \ Parity Error
0x02 == UCSR1A_U2X1 \ Double the USART transmission speed
0x01 == UCSR1A_MPCM1 \ Multi-processor Communication Mode
0xC9 == UCSR1B \ USART Control and Status Register B
0x80 == UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
0x40 == UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
0x20 == UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
0x10 == UCSR1B_RXEN1 \ Receiver Enable
0x08 == UCSR1B_TXEN1 \ Transmitter Enable
0x04 == UCSR1B_UCSZ12 \ Character Size
0x02 == UCSR1B_RXB81 \ Receive Data Bit 8
0x01 == UCSR1B_TXB81 \ Transmit Data Bit 8
0xCA == UCSR1C \ USART Control and Status Register C
0xC0 == UCSR1C_UMSEL1 \ USART Mode Select
0x30 == UCSR1C_UPM1 \ Parity Mode Bits
0x08 == UCSR1C_USBS1 \ Stop Bit Select
0x06 == UCSR1C_UCSZ1 \ Character Size
0x01 == UCSR1C_UCPOL1 \ Clock Polarity
0xCC == UBRR1 \ USART Baud Rate Register Bytes
\ EEPROM
0x41 == EEAR \ EEPROM Address Register Low Bytes
0x40 == EEDR \ EEPROM Data Register
0x3F == EECR \ EEPROM Control Register
0x30 == EECR_EEPM \ EEPROM Programming Mode Bits
0x3 == EERIE
0x2 == EEMWE
0x1 == EEWE
0x0 == EERE
\ TIMER_COUNTER_5
0x120 == TCCR5A \ Timer/Counter5 Control Register A
0xC0 == TCCR5A_COM5A \ Compare Output Mode 1A, bits
0x30 == TCCR5A_COM5B \ Compare Output Mode 5B, bits
0x0C == TCCR5A_COM5C \ Compare Output Mode 5C, bits
0x03 == TCCR5A_WGM5 \ Waveform Generation Mode
0x121 == TCCR5B \ Timer/Counter5 Control Register B
0x80 == TCCR5B_ICNC5 \ Input Capture 5 Noise Canceler
0x40 == TCCR5B_ICES5 \ Input Capture 5 Edge Select
0x18 == TCCR5B_WGM5 \ Waveform Generation Mode
0x07 == TCCR5B_CS5 \ Prescaler source of Timer/Counter 5
0x122 == TCCR5C \ Timer/Counter 5 Control Register C
0x80 == TCCR5C_FOC5A \ Force Output Compare 5A
0x40 == TCCR5C_FOC5B \ Force Output Compare 5B
0x20 == TCCR5C_FOC5C \ Force Output Compare 5C
0x124 == TCNT5 \ Timer/Counter5 Bytes
0x128 == OCR5A \ Timer/Counter5 Output Compare Register A Bytes
0x12A == OCR5B \ Timer/Counter5 Output Compare Register B Bytes
0x12C == OCR5C \ Timer/Counter5 Output Compare Register B Bytes
0x126 == ICR5 \ Timer/Counter5 Input Capture Register Bytes
0x73 == TIMSK5 \ Timer/Counter5 Interrupt Mask Register
0x20 == TIMSK5_ICIE5 \ Timer/Counter5 Input Capture Interrupt Enable
0x08 == TIMSK5_OCIE5C \ Timer/Counter5 Output Compare C Match Interrupt Enable
0x04 == TIMSK5_OCIE5B \ Timer/Counter5 Output Compare B Match Interrupt Enable
0x02 == TIMSK5_OCIE5A \ Timer/Counter5 Output Compare A Match Interrupt Enable
0x01 == TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interrupt Enable
0x3A == TIFR5 \ Timer/Counter5 Interrupt Flag register
0x20 == TIFR5_ICF5 \ Input Capture Flag 5
0x08 == TIFR5_OCF5C \ Output Compare Flag 5C
0x04 == TIFR5_OCF5B \ Output Compare Flag 5B
0x02 == TIFR5_OCF5A \ Output Compare Flag 5A
0x01 == TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
\ TIMER_COUNTER_4
0xA0 == TCCR4A \ Timer/Counter4 Control Register A
0xC0 == TCCR4A_COM4A \ Compare Output Mode 1A, bits
0x30 == TCCR4A_COM4B \ Compare Output Mode 4B, bits
0x0C == TCCR4A_COM4C \ Compare Output Mode 4C, bits
0x03 == TCCR4A_WGM4 \ Waveform Generation Mode
0xA1 == TCCR4B \ Timer/Counter4 Control Register B
0x80 == TCCR4B_ICNC4 \ Input Capture 4 Noise Canceler
0x40 == TCCR4B_ICES4 \ Input Capture 4 Edge Select
0x18 == TCCR4B_WGM4 \ Waveform Generation Mode
0x07 == TCCR4B_CS4 \ Prescaler source of Timer/Counter 4
0xA2 == TCCR4C \ Timer/Counter 4 Control Register C
0x80 == TCCR4C_FOC4A \ Force Output Compare 4A
0x40 == TCCR4C_FOC4B \ Force Output Compare 4B
0x20 == TCCR4C_FOC4C \ Force Output Compare 4C
0xA4 == TCNT4 \ Timer/Counter4 Bytes
0xA8 == OCR4A \ Timer/Counter4 Output Compare Register A Bytes
0xAA == OCR4B \ Timer/Counter4 Output Compare Register B Bytes
0xAC == OCR4C \ Timer/Counter4 Output Compare Register B Bytes
0xA6 == ICR4 \ Timer/Counter4 Input Capture Register Bytes
0x72 == TIMSK4 \ Timer/Counter4 Interrupt Mask Register
0x20 == TIMSK4_ICIE4 \ Timer/Counter4 Input Capture Interrupt Enable
0x08 == TIMSK4_OCIE4C \ Timer/Counter4 Output Compare C Match Interrupt Enable
0x04 == TIMSK4_OCIE4B \ Timer/Counter4 Output Compare B Match Interrupt Enable
0x02 == TIMSK4_OCIE4A \ Timer/Counter4 Output Compare A Match Interrupt Enable
0x01 == TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interrupt Enable
0x39 == TIFR4 \ Timer/Counter4 Interrupt Flag register
0x20 == TIFR4_ICF4 \ Input Capture Flag 4
0x08 == TIFR4_OCF4C \ Output Compare Flag 4C
0x04 == TIFR4_OCF4B \ Output Compare Flag 4B
0x02 == TIFR4_OCF4A \ Output Compare Flag 4A
0x01 == TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
\ TIMER_COUNTER_3
0x90 == TCCR3A \ Timer/Counter3 Control Register A
0xC0 == TCCR3A_COM3A \ Compare Output Mode 1A, bits
0x30 == TCCR3A_COM3B \ Compare Output Mode 3B, bits
0x0C == TCCR3A_COM3C \ Compare Output Mode 3C, bits
0x03 == TCCR3A_WGM3 \ Waveform Generation Mode
0x91 == TCCR3B \ Timer/Counter3 Control Register B
0x80 == TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
0x40 == TCCR3B_ICES3 \ Input Capture 3 Edge Select
0x18 == TCCR3B_WGM3 \ Waveform Generation Mode
0x07 == TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
0x92 == TCCR3C \ Timer/Counter 3 Control Register C
0x80 == TCCR3C_FOC3A \ Force Output Compare 3A
0x40 == TCCR3C_FOC3B \ Force Output Compare 3B
0x20 == TCCR3C_FOC3C \ Force Output Compare 3C
0x94 == TCNT3 \ Timer/Counter3 Bytes
0x98 == OCR3A \ Timer/Counter3 Output Compare Register A Bytes
0x9A == OCR3B \ Timer/Counter3 Output Compare Register B Bytes
0x9C == OCR3C \ Timer/Counter3 Output Compare Register B Bytes
0x96 == ICR3 \ Timer/Counter3 Input Capture Register Bytes
0x71 == TIMSK3 \ Timer/Counter3 Interrupt Mask Register
0x20 == TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
0x08 == TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
0x04 == TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
0x02 == TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
0x01 == TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
0x38 == TIFR3 \ Timer/Counter3 Interrupt Flag register
0x20 == TIFR3_ICF3 \ Input Capture Flag 3
0x08 == TIFR3_OCF3C \ Output Compare Flag 3C
0x04 == TIFR3_OCF3B \ Output Compare Flag 3B
0x02 == TIFR3_OCF3A \ Output Compare Flag 3A
0x01 == TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
\ TIMER_COUNTER_1
0x80 == TCCR1A \ Timer/Counter1 Control Register A
0xC0 == TCCR1A_COM1A \ Compare Output Mode 1A, bits
0x30 == TCCR1A_COM1B \ Compare Output Mode 1B, bits
0x0C == TCCR1A_COM1C \ Compare Output Mode 1C, bits
0x03 == TCCR1A_WGM1 \ Waveform Generation Mode
0x81 == TCCR1B \ Timer/Counter1 Control Register B
0x80 == TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
0x40 == TCCR1B_ICES1 \ Input Capture 1 Edge Select
0x18 == TCCR1B_WGM1 \ Waveform Generation Mode
0x07 == TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
0x82 == TCCR1C \ Timer/Counter 1 Control Register C
0x80 == TCCR1C_FOC1A \ Force Output Compare 1A
0x40 == TCCR1C_FOC1B \ Force Output Compare 1B
0x20 == TCCR1C_FOC1C \ Force Output Compare 1C
0x84 == TCNT1 \ Timer/Counter1 Bytes
0x88 == OCR1A \ Timer/Counter1 Output Compare Register A Bytes
0x8A == OCR1B \ Timer/Counter1 Output Compare Register B Bytes
0x8C == OCR1C \ Timer/Counter1 Output Compare Register C Bytes
0x86 == ICR1 \ Timer/Counter1 Input Capture Register Bytes
0x6F == TIMSK1 \ Timer/Counter1 Interrupt Mask Register
0x20 == TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
0x08 == TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
0x04 == TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
0x02 == TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
0x01 == TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
0x36 == TIFR1 \ Timer/Counter1 Interrupt Flag register
0x20 == TIFR1_ICF1 \ Input Capture Flag 1
0x08 == TIFR1_OCF1C \ Output Compare Flag 1C
0x04 == TIFR1_OCF1B \ Output Compare Flag 1B
0x02 == TIFR1_OCF1A \ Output Compare Flag 1A
0x01 == TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
\ JTAG
0x51 == OCDR \ On-Chip Debug Related Register in I/O Memory
0x55 == MCUCR \ MCU Control Register
0x80 == MCUCR_JTD \ JTAG Interface Disable
0x54 == MCUSR \ MCU Status Register
0x10 == MCUSR_JTRF \ JTAG Reset Flag
\ EXTERNAL_INTERRUPT
0x69 == EICRA \ External Interrupt Control Register A
0xC0 == EICRA_ISC3 \ External Interrupt Sense Control Bit
0x30 == EICRA_ISC2 \ External Interrupt Sense Control Bit
0x0C == EICRA_ISC1 \ External Interrupt Sense Control Bit
0x03 == EICRA_ISC0 \ External Interrupt Sense Control Bit
0x6A == EICRB \ External Interrupt Control Register B
0xC0 == EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
0x30 == EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
0x0C == EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
0x03 == EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
0x3D == EIMSK \ External Interrupt Mask Register
0xFF == EIMSK_INT \ External Interrupt Request 7 Enable
0x3C == EIFR \ External Interrupt Flag Register
0xFF == EIFR_INTF \ External Interrupt Flags
0x6D == PCMSK2 \ Pin Change Mask Register 2
0x6C == PCMSK1 \ Pin Change Mask Register 1
0x6B == PCMSK0 \ Pin Change Mask Register 0
0x3B == PCIFR \ Pin Change Interrupt Flag Register
0x07 == PCIFR_PCIF \ Pin Change Interrupt Flags
0x68 == PCICR \ Pin Change Interrupt Control Register
0x07 == PCICR_PCIE \ Pin Change Interrupt Enables
\ CPU
0x5F == SREG \ Status Register
0x80 == SREG_I \ Global Interrupt Enable
0x40 == SREG_T \ Bit Copy Storage
0x20 == SREG_H \ Half Carry Flag
0x10 == SREG_S \ Sign Bit
0x08 == SREG_V \ Two's Complement Overflow Flag
0x04 == SREG_N \ Negative Flag
0x02 == SREG_Z \ Zero Flag
0x01 == SREG_C \ Carry Flag
0x5D == SPL
0x5E == SPH
0x74 == XMCRA \ External Memory Control Register A
0x80 == XMCRA_SRE \ External SRAM Enable
0x70 == XMCRA_SRL \ Wait state page limit
0x0C == XMCRA_SRW1 \ Wait state select bit upper page
0x03 == XMCRA_SRW0 \ Wait state select bit lower page
0x75 == XMCRB \ External Memory Control Register B
0x80 == XMCRB_XMBK \ External Memory Bus Keeper Enable
0x07 == XMCRB_XMM \ External Memory High Mask
0x66 == OSCCAL \ Oscillator Calibration Value
0x61 == CLKPR \
0x80 == CLKPR_CLKPCE \
0x0F == CLKPR_CLKPS \
0x53 == SMCR \ Sleep Mode Control Register
0x0E == SMCR_SM \ Sleep Mode Select bits
0x01 == SMCR_SE \ Sleep Enable
0x5C == EIND \ Extended Indirect Register
0x5B == RAMPZ \ RAM Page Z Select Register
0x4B == GPIOR2 \ General Purpose IO Register 2
0xFF == GPIOR2_GPIOR \ General Purpose IO Register 2 bis
0x4A == GPIOR1 \ General Purpose IO Register 1
0xFF == GPIOR1_GPIOR \ General Purpose IO Register 1 bis
0x3E == GPIOR0 \ General Purpose IO Register 0
0x80 == GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
0x40 == GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
0x20 == GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
0x10 == GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
0x08 == GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
0x04 == GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
0x02 == GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
0x01 == GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
0x65 == PRR1 \ Power Reduction Register1
0x20 == PRR1_PRTIM5 \ Power Reduction Timer/Counter5
0x10 == PRR1_PRTIM4 \ Power Reduction Timer/Counter4
0x08 == PRR1_PRTIM3 \ Power Reduction Timer/Counter3
0x07 == PRR1_PRUSART \ Power Reduction USART3
0x64 == PRR0 \ Power Reduction Register0
0x80 == PRR0_PRTWI \ Power Reduction TWI
0x40 == PRR0_PRTIM2 \ Power Reduction Timer/Counter2
0x20 == PRR0_PRTIM0 \ Power Reduction Timer/Counter0
0x08 == PRR0_PRTIM1 \ Power Reduction Timer/Counter1
0x04 == PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
0x02 == PRR0_PRUSART0 \ Power Reduction USART
0x01 == PRR0_PRADC \ Power Reduction ADC
\ AD_CONVERTER
0x7C == ADMUX \ The ADC multiplexer Selection Register
0xC0 == ADMUX_REFS \ Reference Selection Bits
0x20 == ADMUX_ADLAR \ Left Adjust Result
0x1F == ADMUX_MUX \ Analog Channel and Gain Selection Bits
0x78 == ADC \ ADC Data Register Bytes
0x7A == ADCSRA \ The ADC Control and Status register A
0x80 == ADCSRA_ADEN \ ADC Enable
0x40 == ADCSRA_ADSC \ ADC Start Conversion
0x20 == ADCSRA_ADATE \ ADC Auto Trigger Enable
0x10 == ADCSRA_ADIF \ ADC Interrupt Flag
0x08 == ADCSRA_ADIE \ ADC Interrupt Enable
0x07 == ADCSRA_ADPS \ ADC Prescaler Select Bits
0x7D == DIDR2 \ Digital Input Disable Register
0x80 == DIDR2_ADC15D \
0x40 == DIDR2_ADC14D \
0x20 == DIDR2_ADC13D \
0x10 == DIDR2_ADC12D \
0x08 == DIDR2_ADC11D \
0x04 == DIDR2_ADC10D \
0x02 == DIDR2_ADC9D \
0x01 == DIDR2_ADC8D \
0x7E == DIDR0 \ Digital Input Disable Register
0x80 == DIDR0_ADC7D \
0x40 == DIDR0_ADC6D \
0x20 == DIDR0_ADC5D \
0x10 == DIDR0_ADC4D \
0x08 == DIDR0_ADC3D \
0x04 == DIDR0_ADC2D \
0x02 == DIDR0_ADC1D \
0x01 == DIDR0_ADC0D \
\ BOOT_LOAD
0x57 == SPMCSR \ Store Program Memory Control Register
0x7 == SPMIE
0x6 == RWWSB
0x4 == RWWSRE
0x3 == BLBSET
0x2 == PGWRT
0x1 == PGERS
0x0 == SPMEN
\ USART2
0xD4 == UDR2 \ USART I/O Data Register
0xD0 == UCSR2A \ USART Control and Status Register A
0x80 == UCSR2A_RXC2 \ USART Receive Complete
0x40 == UCSR2A_TXC2 \ USART Transmitt Complete
0x20 == UCSR2A_UDRE2 \ USART Data Register Empty
0x10 == UCSR2A_FE2 \ Framing Error
0x08 == UCSR2A_DOR2 \ Data overRun
0x04 == UCSR2A_UPE2 \ Parity Error
0x02 == UCSR2A_U2X2 \ Double the USART transmission speed
0x01 == UCSR2A_MPCM2 \ Multi-processor Communication Mode
0xD1 == UCSR2B \ USART Control and Status Register B
0x80 == UCSR2B_RXCIE2 \ RX Complete Interrupt Enable
0x40 == UCSR2B_TXCIE2 \ TX Complete Interrupt Enable
0x20 == UCSR2B_UDRIE2 \ USART Data register Empty Interrupt Enable
0x10 == UCSR2B_RXEN2 \ Receiver Enable
0x08 == UCSR2B_TXEN2 \ Transmitter Enable
0x04 == UCSR2B_UCSZ22 \ Character Size
0x02 == UCSR2B_RXB82 \ Receive Data Bit 8
0x01 == UCSR2B_TXB82 \ Transmit Data Bit 8
0xD2 == UCSR2C \ USART Control and Status Register C
0xC0 == UCSR2C_UMSEL2 \ USART Mode Select
0x30 == UCSR2C_UPM2 \ Parity Mode Bits
0x08 == UCSR2C_USBS2 \ Stop Bit Select
0x06 == UCSR2C_UCSZ2 \ Character Size
0x01 == UCSR2C_UCPOL2 \ Clock Polarity
0xD4 == UBRR2 \ USART Baud Rate Register Bytes
\ USART3
0x136 == UDR3 \ USART I/O Data Register
0x130 == UCSR3A \ USART Control and Status Register A
0x80 == UCSR3A_RXC3 \ USART Receive Complete
0x40 == UCSR3A_TXC3 \ USART Transmitt Complete
0x20 == UCSR3A_UDRE3 \ USART Data Register Empty
0x10 == UCSR3A_FE3 \ Framing Error
0x08 == UCSR3A_DOR3 \ Data overRun
0x04 == UCSR3A_UPE3 \ Parity Error
0x02 == UCSR3A_U2X3 \ Double the USART transmission speed
0x01 == UCSR3A_MPCM3 \ Multi-processor Communication Mode
0x131 == UCSR3B \ USART Control and Status Register B
0x80 == UCSR3B_RXCIE3 \ RX Complete Interrupt Enable
0x40 == UCSR3B_TXCIE3 \ TX Complete Interrupt Enable
0x20 == UCSR3B_UDRIE3 \ USART Data register Empty Interrupt Enable
0x10 == UCSR3B_RXEN3 \ Receiver Enable
0x08 == UCSR3B_TXEN3 \ Transmitter Enable
0x04 == UCSR3B_UCSZ32 \ Character Size
0x02 == UCSR3B_RXB83 \ Receive Data Bit 8
0x01 == UCSR3B_TXB83 \ Transmit Data Bit 8
0x132 == UCSR3C \ USART Control and Status Register C
0xC0 == UCSR3C_UMSEL3 \ USART Mode Select
0x30 == UCSR3C_UPM3 \ Parity Mode Bits
0x08 == UCSR3C_USBS3 \ Stop Bit Select
0x06 == UCSR3C_UCSZ3 \ Character Size
0x01 == UCSR3C_UCPOL3 \ Clock Polarity
0x134 == UBRR3 \ USART Baud Rate Register Bytes
\ Interrupts
( INTERRUPT VECTORS )
S" isr.spf" INCLUDED
0x0 ORG
INTERRUPT RESET
INTERRUPT INT0Addr \ External Interrupt Request 0
INTERRUPT INT1Addr \ External Interrupt Request 1
INTERRUPT INT2Addr \ External Interrupt Request 2
INTERRUPT INT3Addr \ External Interrupt Request 3
INTERRUPT INT4Addr \ External Interrupt Request 4
INTERRUPT INT5Addr \ External Interrupt Request 5
INTERRUPT INT6Addr \ External Interrupt Request 6
INTERRUPT INT7Addr \ External Interrupt Request 7
INTERRUPT PCINT0Addr \ Pin Change Interrupt Request 0
INTERRUPT PCINT1Addr \ Pin Change Interrupt Request 1
INTERRUPT PCINT2Addr \ Pin Change Interrupt Request 2
INTERRUPT WDTAddr \ Watchdog Time-out Interrupt
INTERRUPT TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
INTERRUPT TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
INTERRUPT TIMER2_OVFAddr \ Timer/Counter2 Overflow
INTERRUPT TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
INTERRUPT TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
INTERRUPT TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
INTERRUPT TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
INTERRUPT TIMER1_OVFAddr \ Timer/Counter1 Overflow
INTERRUPT TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
INTERRUPT TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
INTERRUPT TIMER0_OVFAddr \ Timer/Counter0 Overflow
INTERRUPT SPI__STCAddr \ SPI Serial Transfer Complete
INTERRUPT USART0__RXAddr \ USART0, Rx Complete
INTERRUPT USART0__UDREAddr \ USART0 Data register Empty
INTERRUPT USART0__TXAddr \ USART0, Tx Complete
INTERRUPT ANALOG_COMPAddr \ Analog Comparator
INTERRUPT ADCAddr \ ADC Conversion Complete
INTERRUPT EE_READYAddr \ EEPROM Ready
INTERRUPT TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
INTERRUPT TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
INTERRUPT TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
INTERRUPT TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
INTERRUPT TIMER3_OVFAddr \ Timer/Counter3 Overflow
INTERRUPT USART1__RXAddr \ USART1, Rx Complete
INTERRUPT USART1__UDREAddr \ USART1 Data register Empty
INTERRUPT USART1__TXAddr \ USART1, Tx Complete
INTERRUPT TWIAddr \ 2-wire Serial Interface
INTERRUPT SPM_READYAddr \ Store Program Memory Read
INTERRUPT TIMER4_CAPTAddr \ Timer/Counter4 Capture Event
INTERRUPT TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
INTERRUPT TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
INTERRUPT TIMER4_COMPCAddr \ Timer/Counter4 Compare Match C
INTERRUPT TIMER4_OVFAddr \ Timer/Counter4 Overflow
INTERRUPT TIMER5_CAPTAddr \ Timer/Counter5 Capture Event
INTERRUPT TIMER5_COMPAAddr \ Timer/Counter5 Compare Match A
INTERRUPT TIMER5_COMPBAddr \ Timer/Counter5 Compare Match B
INTERRUPT TIMER5_COMPCAddr \ Timer/Counter5 Compare Match C
INTERRUPT TIMER5_OVFAddr \ Timer/Counter5 Overflow
INTERRUPT USART2__RXAddr \ USART2, Rx Complete
INTERRUPT USART2__UDREAddr \ USART2 Data register Empty
INTERRUPT USART2__TXAddr \ USART2, Tx Complete
INTERRUPT USART3__RXAddr \ USART3, Rx Complete
INTERRUPT USART3__UDREAddr \ USART3 Data register Empty
INTERRUPT USART3__TXAddr \ USART3, Tx Complete
S" init.spf" INCLUDED
При присвоении BASE значения происходит беда.
ЗЫ DEPTH выдаёт 0x20FF ?