Вот, для процессоров. Интерфейс надо адаптировать к конкретному решению, конечно, но тут видно, в какой момент и откуда забирать данные и куда их подавать.

[code]library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity uart is
generic ( FCORE : integer := 100000000;
UART_BAUDRATE : integer := 115200
);
Port ( clk : in STD_LOGIC;
rx : in STD_LOGIC;
tx : out STD_LOGIC;
txe : in STD_LOGIC; -- start transmit
received : out STD_LOGIC_VECTOR (7 downto 0);
transmit : in STD_LOGIC_VECTOR (7 downto 0));
end uart;

architecture Behavioral of uart is

signal rxstate, txstate : integer range 0 to (FCORE * 12) / UART_BAUDRATE := 0;

begin

process(clk)
begin
if clk'event and clk = '1' then
case rxstate is
when 0 to FCORE / 2 / UART_BAUDRATE => if rx = '0' then rxstate <= rxstate + 1; end if;
when 3 * FCORE / 2 / UART_BAUDRATE => received(0) <= rx; rxstate <= rxstate + 1;
when 5 * FCORE / 2 / UART_BAUDRATE => received(1) <= rx; rxstate <= rxstate + 1;
when 7 * FCORE / 2 / UART_BAUDRATE => received(2) <= rx; rxstate <= rxstate + 1;
when 9 * FCORE / 2 / UART_BAUDRATE => received(3) <= rx; rxstate <= rxstate + 1;
when 11 * FCORE / 2 / UART_BAUDRATE => received(4) <= rx; rxstate <= rxstate + 1;
when 13 * FCORE / 2 / UART_BAUDRATE => received(5) <= rx; rxstate <= rxstate + 1;
when 15 * FCORE / 2 / UART_BAUDRATE => received(6) <= rx; rxstate <= rxstate + 1;
when 17 * FCORE / 2 / UART_BAUDRATE => received(7) <= rx; rxstate <= rxstate + 1;
when 19 * FCORE / 2 / UART_BAUDRATE => rxstate <= 0; -- rxcounter <= rxcounter + 1;
when others => rxstate <= rxstate + 1;
end case;
end if;
end process;

process(clk)
begin
if clk'event and clk = '1' then
case txstate is
when 0 => tx <= '1';
if txe = '1' then txstate <= 1; end if;
when 1 => tx <= '0'; txstate <= txstate + 1;
when FCORE / UART_BAUDRATE => tx <= transmit(0); txstate <= txstate + 1;
when 2 * FCORE / UART_BAUDRATE => tx <= transmit(1); txstate <= txstate + 1;
when 3 * FCORE / UART_BAUDRATE => tx <= transmit(2); txstate <= txstate + 1;
when 4 * FCORE / UART_BAUDRATE => tx <= transmit(3); txstate <= txstate + 1;
when 5 * FCORE / UART_BAUDRATE => tx <= transmit(4); txstate <= txstate + 1;
when 6 * FCORE / UART_BAUDRATE => tx <= transmit(5); txstate <= txstate + 1;
when 7 * FCORE / UART_BAUDRATE => tx <= transmit(6); txstate <= txstate + 1;
when 8 * FCORE / UART_BAUDRATE => tx <= transmit(7); txstate <= txstate + 1;
when 9 * FCORE / UART_BAUDRATE => tx <= '1'; txstate <= txstate + 1;
when 11 * FCORE / UART_BAUDRATE => txstate <= 0;
when others => txstate <= txstate + 1;
end case;
end if;
end process;


end Behavioral;[/code]